View HCPL-0700_85016.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700
DESCRIPTION
The HCPL-0700 and HCPL-0701 optocouplers consist of an AlGaAs LED optically coupled to a high gain split darlington photodetector housed in a compact 8-pin small outline package. The split darlington configuration separating the input photodiode and the first stage gain from the output transistor permits lower output saturation voltage and higher speed operation than possible with conventional darlington phototransistor optocoupler. The combination of a very low input current of 0.5 mA and a high current transfer ratio of 2000% makes this family particularly useful for input interface to MOS, CMOS, LSTTL and EIA RS232C, while output compatibility is ensured to CMOS as well as high fan-out TTL requirements.
HCPL-0701
FEATURES
* * * * * Low current - 0.5 mA Superior CTR-2000% Superior CMR-10 kV/s CTR guaranteed 0-70C *BSI, CSA and UL approval
SEATING PLANE
PACKAGE DIMENSIONS
0.164 (4.16) 0.144 (3.66)
APPLICATIONS
* * * * Digital logic ground isolation Telephone ring detector EIA-RS-232C line receiver High common mode noise line receiver * P bus isolation * Current loop receiver
Pin 1
0.202 (5.13) 0.182 (4.63)
0.019 (0.48) 0.010 (0.25) 0.006 (0.16)
N/C 1
8 VCC
0.143 (3.63) 0.123 (3.13)
+2 VF _ 3
7 VB
6 VO
0.021 (0.53) 0.011 (0.28)
0.008 (0.20) 0.003 (0.08) 0.050 (1.27) TYP
0.244 (6.19) 0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
N/C 4 5 GND
HCPL-0700 / HCPL-0701
NOTE All dimensions are in inches (millimeters)
(c) 2003 Fairchild Semiconductor Corporation
Page 1 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise specified)
Parameter Storage Temperature Operating Temperature Reflow Temperature Profile (Refer to fig. 11) EMITTER DC/Average Forward Input Current Peak Forward Input Current (50% duty cycle, 1 ms P.W.) Peak Transient Input Current - (1 s P.W., 300 pps) Reverse Input Voltage Input Power Dissipation DETECTOR Average Output Current (Pin 6) Emitter-Base Reverse Voltage Supply Voltage, Output Voltage Output power dissipation *Samples submitted for certification - Approval pending HCPL-0700 HCPL-0701 IO (avg) VEBR VCC, VO PD 60 0.5 -0.5 to 7 -0.5 to 18 100 mA V V mW IF (avg) IF (pk) IF (trans) VR PD 20 40 1.0 5 35 mA mA A V mW Symbol TSTG TOPR Value -55 to +125 -55 to +85 Units C C
ELECTRICAL CHARACTERISTICS (TA = 0 to 70C Unless otherwise specified) INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter EMITTER Input Forward Voltage Input Reverse Breakdown Voltage Temperature coefficient of forward voltage DETECTOR Logic high output current Logic low supply Logic high supply Test Conditions (TA =25C) (IF = 1.6 mA) (TA =25C, IR = 10 A) (IF = 0 mA, VO = VCC = 18 V) (IF = 0 mA, VO = VCC = 7 V) (IF = 1.6 mA, VO = Open) (VCC = 18 V) (IF = 0 mA, VO = Open) (VCC = 18 V) Symbol VF BVR Device All All All HCPL-0701 HCPL-0700 HCPL-0700 HCPL-0701 HCPL-0700 HCPL-0701 Min 1.0 5.0 Typ** 1.27 20 -1.8 0.01 0.01 0.4 0.05 100 250 1.5 10 mV/C A mA A Max 1.7 1.75 V Unit
(IF = 1.6 mA) (VF/TA) IOH ICCL ICCH
(c) 2003 Fairchild Semiconductor Corporation
Page 2 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
TRANSFER CHARACTERISTICS (TA = 0 to 70C Unless otherwise specified)
Parameter COUPLED Current transfer ratio (Notes 1,2) Test Conditions Symbol (IF = 0.5 mA, VO = 0.4 V, VCC = 4.5V) (IF = 1.6 mA, VO = 0.4 V, VCC = 4.5V) (IF = 1.6 mA, VO = 0.4 V, VCC = 4.5V) (IF = 0.5 mA, IO = 2 mA, VCC = 4.5V) Logic low output voltage output voltage (IF = 1.6 mA, IO = 8 mA, VCC = 4.5V) (IF = 5 mA, IO = 15 mA, VCC = 4.5V) (IF = 12 mA, IO = 24 mA, VCC = 4.5V) (IF = 1.6 mA, IO = 4.8 mA, VCC = 4.5V) HCPL-0700 VOL HCPL-0701 CTR Device HCPL-0701 HCPL-0701 HCPL-0700 Min 400 500 300 Typ** 2000 1300 1300 0.05 0.10 0.13 0.20 0.08 Max 5000 2600 2600 0.4 0.4 0.4 0.4 0.4 V % Unit
ISOLATION CHARACTERISTICS (TA = 0 to 70C Unless otherwise specified)
Characteristics Input-output insulation leakage current Test Conditions (Relative humidity = 45%) (TA = 25C, t = 5 s) (VI-O = 3000 VDC) (Note 4) (RH 50%, TA = 25C) (Note 4, 5) ( t = 1 min.) (Note 4) (VI-O = 500 VDC) Symbol Min Typ** Max Unit
II-O
1.0
A
Withstand insulation test voltage Resistance (input to output) ** All typicals at TA = 25C
VISO RI-O
2500 1012
VRMS
(c) 2003 Fairchild Semiconductor Corporation
Page 3 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
SWITCHING CHARACTERISTICS (TA = 0 to 70C unless otherwise specified., VCC = 5 V)
Parameter Test Conditions (RL = 4.7 k, IF = 0.5 mA) TA = 25C Propagation delay time to logic low (Note 2) (Fig. 13) (RL = 270 , IF = 12 mA) TA = 25C (RL = 2.2 k, IF = 1.6 mA) TA = 25C (RL = 4.7 k, IF = 0.5 mA) (RL = 4.7 k, IF = 0.5 mA) TA = 25C Propagation delay time to logic high (Note 2) (Fig. 13) (RL = 270 , IF = 12 mA) TA = 25C (RL = 2.2 k, IF = 1.6 mA) TA = 25C Common mode transient immunity at logic high Common mode transient immunity at logic low (IF = 0 mA, |VCM| = 10 VP-P) TA = 25C (RL = 2.2 k) (Note 3) (Fig. 14) (IF = 1.6 mA, |VCM| = 10 VP-P, RL = 2.2 k) TA = 25C (Note 3) (Fig. 14) |CMH| TPLH TPHL Symbol Device HCPL-0701 HCPL-0701 HCPL-0700 HCPL-0701 HCPL-0701 HCPL-0700 HCPL-0700 HCPL-0701 HCPL-0700 |CML| HCPL-0701 1,000 10,000 V/s 1,000 10,000 V/s Min Typ** 4 0.2 1.5 12 1.3 7 Max 30 25 2 1 15 10 90 60 10 7 50 35 s s Unit
NOTES 1. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%. 2. Pin 7 open. Use of a resistor between pins 5 and 7 will decrease gain and delay time. 3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM/dt on the leading edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V). 4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 5. 2500 VAC RMS for 1 minute duration is equivalent to 3000 VAC RMS for 1 second duration. ** All typicals at TA = 25C
(c) 2003 Fairchild Semiconductor Corporation
Page 4 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
ELECTRICAL CHARACTERISTICS (TA = 0 to 70C unless otherwise specified)
Current Limiting Resistor Calculations V DD1 - V DF - V OL1 R 1 (Non-Invert) = -------------------------------------------------IF V DD1 - V OH1 - V DF R 1 (Invert) = -------------------------------------------------IF V DD2 = V OLX ( @I L - I 2 ) R 2 = ---------------------------------------------------------------IL Where: VDD1 VDD2 VDF VOL1 VOH1 IF VOLX IL I2 Input Supply Voltage Output Supply Voltage Diode Forward Voltage Logic "0" Voltage of Driver Logic "1" Voltage of Driver Diode Forward Current Saturation Voltage of Output Transistor Load Current Through Resistor R2 Input Current of Output Gate
INPUT CMOS @ 5V R1 () CMOS @5V CMOS @ 10 V 74XX 74LXX 74SXX 74LSXX 74HXX NON-INV. INV. NON-INV. INV. NON-INV. INV. NON-INV. INV. NON-INV. INV. NON-INV. INV. NON-INV. INV. 2000 510 5100 4700 2200 180 1800 100 2000 360 2000 180 2000 180 R2 () CMOS @ 10V R2 () 74XX R2 () OUTPUT 74LXX R2 () 74SXX 74LSXX 74HXX R2 () R2 () R2 ()
1000
2200
750
1000
1000
1000
560
Fig. 1 Resistor Values for Logic Interface
VDD1 VDD2 VDD2
1 2 3
IN R1
8 7 6
OUT R1 R2 IN
1 2 3 4
8 7 6 5
R2
OUT
4
5
Fig. 2 Non-Inverting Logic Interface
(c) 2003 Fairchild Semiconductor Corporation
Fig. 3 Inverting Logic Interface
Page 5 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700
TYPICAL PERFORMANCE CURVES
Fig. 4 Propagation Delay vs. Temperature
35 30 VCC = 5 V IF = 0.5 mA RL = 4.7 k 1/f = 50 s 20 18 IF = 1.6 mA VCC = 5 V RL = 2.2 k 1/f = 50 s
HCPL-0701
Fig. 5 Propagation Delay vs. Temperature
tp - PROPAGATION DELAY (s)
tp - PROPAGATION DELAY (s)
tPLH
tPLH
16 14 12 10 8 6 4
25
20
15
10
5 tPHL 0 -60 -40 -20 0 20 40 60 80 100 2 0 -60 -40 -20 0 20 40 60 80
tPHL
100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
Fig. 6 Propagation Delay vs. Temperature
IF = 12 mA VCC = 5 V RL = 270 1/f = 50 s
Fig. 7 Logic High Output Current vs. Temperature
IOH - LOGIC HIGH OUTPUT CURRENT (nA)
1000 VCC = VO = 5.5 V
4
tp - PROPAGATION DELAY (s)
tPLH
3
100
10
2
1
1 tPHL 0 -60 -40 -20 0 20 40 60 80 100
0.1
0.01 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
(c) 2003 Fairchild Semiconductor Corporation
Page 6 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700
TYPICAL PERFORMANCE CURVES
Fig. 8 Output Current vs. Input Forward Current
100 100
HCPL-0701
Fig. 9 Input Forward Current vs. Forward Voltage
IF - FORWARD CURRENT (mA)
TA = 85C 10 TA = 70C
IO - OUTPUT CURRENT (mA)
10
TA = 85C
1
1 TA = 70C TA = 25C 0.1 TA = 0C TA = -40C 0.01 0.01 VCC = 5V VO = 0.4V 10
0.1 TA = 25C 0.01 TA = 0C TA = -40C 0.001 1.1 1.2 1.3 1.4 1.5 1.6
0.1
1
IF - INPUT FORWARD CURRENT (mA)
VF - FORWARD VOLTAGE (V)
Fig. 10 Logic Low Supply Current vs. Input Forward Current
ICCL - LOGIC LOW SUPPLY CURRENT (mA)
0.5 Logic Low Supply Current vs. Input Forward Current 0.4 VCC = 18V 80
Fig. 11 DC Transfer Characteristics
IO - OUTPUT CURRENT (mA)
60
IF = 5.0mA IF = 4.5mA IF = 4.0mA IF = 3.5mA IF = 3.0mA IF = 2.5mA VCC= 5V TA = 25C IF = 2.0mA IF = 1.5mA IF = 1.0mA IF = 0.5mA
0.3 VCC = 5V 0.2
40
20
0.1
0.0 0.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 1 2
IF - INPUT FORWARD CURRENT (mA)
VO - OUTPUT VOLTAGE (V)
Fig. 12 Current Transfer Ratio vs. Input Forward Current
3500
CTR - CURRENT TRANSFER RATIO (%)
3000
TA = 85C
VCC = 5V VO = 0.4V
2500
TA = 70C TA = 25C
2000
1500
TA = 0C
1000 TA = -40C 500
0 0.1
1
10
IF - INPUT FORWARD CURRENT (mA)
(c) 2003 Fairchild Semiconductor Corporation
Page 7 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
Pulse Generator I F tr = 5ns Z O = 50 10% D.C. I/f < 100s
1
+
Noise Shield
8 7 6 5
VCC
IF +5 V 0
2
VF -
VB
RL
VO VO
5V
3
I F Monitor Rm
VO 0.1 F
1.5 V
1.5 V VOL
4
GND
C L = 15 pF*
TPHL
TPLH
* Includes probe and fixture capacitance
Fig. 13 Switching Time Test Circuit T
IF
1
+
Noise Shield
VCM 10 V
90% 10% tr
90% 10% tf
8 7 6 5
VCC
+5 V 0V
2
A B VFF VF -
VB
RL
3 4
+
VCM
VO 0.1 F GND
VO VO Switch at A : I F = 0 mA VO 5V
-
VOL
Switch at B : I F = 1.6 mA
Pulse Gen
Fig. 14 Common Mode Immunity T Test Circuit
(c) 2003 Fairchild Semiconductor Corporation
Page 8 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700
ORDERING INFORMATION
Option V R1 R1V R2 R2V Order Entry Identifier V R1 R1V R2 R2V Description VDE 0884 Tape and reel (500 units per reel) VDE 0884, Tape and reel (500 units per reel) Tape and reel (2500 units per reel) VDE 0884, Tape and reel (2500 units per reel)
HCPL-0701
MARKING INFORMATION
1
0700 V X YY S
2
6
3
4
5
Definitions
1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) One digit year code, e.g., `3' Two digit work week ranging from `01' to `53' Assembly package code
(c) 2003 Fairchild Semiconductor Corporation
Page 9 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700
Carrier Tape Specifications
8.0 0.1 3.5 0.2 0.3 MAX 4.0 0.1 2 0.05 O1.5 MIN 1.75 0.10
HCPL-0701
5.5 0.05 8.3 0.1 5.2 0.2 12.0 0.3
0.1 MAX User Direction of Feed
6.4 0.2
O1.5 + 0.1/-0
Reflow Profile
300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 245C peak
230C, 10-30 s
Time above 183C, 120-180 sec Ramp up = 2-10C/sec * Peak reflow temperature: 245C (package surface temperature) * Time of temperature higher than 183C for 120-180 seconds * One time soldering reflow is recommended 3.5 4 4.5
3
Time (Minute)
(c) 2003 Fairchild Semiconductor Corporation
Page 10 of 11
8/18/03
LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
HCPL-0700 HCPL-0701
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2003 Fairchild Semiconductor Corporation
Page 11 of 11
8/18/03

▲Up To Search▲

Price & Availability of HCPL-0700

	To Download HCPL-0700 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .